The SiSoft SANDRA test suite database clarified the layout of AMD EPYC Rome multi-core processors based on Zen 2 architecture.
In particular, AMD's EPYC Rome 64-core processor consists of eight separate crystals of 8 Zen 2 cores, manufactured according to the 7-nanometer process standards. These processor units are combined into a common substrate using an I / O unit, which is manufactured using a 14 nm process technology and provides communication between the processor and memory and PCIe lines. As a result, the cache hierarchy is mentioned, which includes 512 KB of second level cache for each core and 16 16 MB blocks of third level cache – 16 x 16 MB L3.
Note that SiSoft SANDRA "sees" the L3 cache distribution. For example, for a Ryzen 7 2700X 8-core processor, a third-level cache is displayed as a "2 x 8 MB L3" construction, which actually corresponds to 8 MB of cache for each 4-core CCX module. Thus, we can conclude that each of the 8-core processor units on the AMD EPYC Rome chip contains two separate 4-core CCX modules with 16 MB third-level cache memory for each. This duplication of the L3 cache per CCX module will allow the processor to better control the data transfer between the computation blocks and the I / O controller. This becomes a very important task, since the I / O controller is now integrated to an 8-channel DDR4 memory controller.